Several emerging petascale architectures use energy-efficient processors with vectorized
computational units and in-order thread processing. On these architectures
the sustained performance of streaming numerical kernels, ubiquitous in the solution
of partial differential equations, represents a formidable challenge despite the regularity
of memory access. Sophisticated optimization techniques beyond the capabilities
of modern compilers are required to fully utilize the Central Processing Unit (CPU).
The aim of the work presented here is to improve the performance of streaming
numerical kernels on high performance architectures by developing efficient algorithms to utilize the vectorized
floating point units. The importance of the development time demands the creation of tools to enable simple yet direct development in assembly to
utilize the power-efficient cores featuring in-order execution and multiple-issue units.
We implement several stencil kernels for a variety of cached memory scenarios using
our Python instruction simulation and generation tool. Our technique simplifies
the development of efficient assembly code for the IBM Blue Gene/P supercomputer's
PowerPC 450. This enables us to perform high-level design, construction, verification, and simulation on a subset of the CPU's instruction set. Our framework has
the capability to implement streaming numerical kernels on current and future high
performance architectures. Finally, we present several automatically generated implementations,
including a 27-point stencil achieving a 1.7x speedup over the best
previously published results.
|Date of Award||Jul 2011|
|Original language||English (US)|
- Computer, Electrical and Mathematical Science and Engineering
|Supervisor||David Keyes (Supervisor)|