Current CMOS-based technologies are facing design challenges related to the continuous scaling down of the minimum feature size, according to Moore’s law. Moreover, conventional computing architecture is no longer an effective way of fulfilling modern applications demands, such as big data analysis, pattern recognition, and vector processing. Therefore, there is an exigent need to shift to new technologies, at both the architecture and the device levels. Recently, memristor devices and structures attracted attention for being promising candidates for this job. Memristor device adds a new dimension for designing novel circuits and systems. In addition, high-density memristor-based crossbar is widely considered to be the essential element for future memory and bio-inspired computing systems. However, numerous challenges need to be addressed before the memristor genuinely replaces current memory and computing technologies, which is the motivation behind this research effort.
In order to address the technology challenges, we begin by fabricating and modeling the memristor device. The devices fabricated at our local clean room enriched our understanding of the memristive phenomenon and enabled the experimental testing for our memristor-based circuits. Moreover, our proposed mathematical modeling for memristor behavior is an essential element for the theoretical circuit design stage. Designing and addressing the challenges of memristor systems with practical complexity, however, requires an extra step, which takes the form of a reliable and modular simulation platform. We, therefore, built a new simulation platform for the resistive crossbar, which can simulate realistic size arrays filled with real memory data. In addition, this simulation platform includes various crossbar nonidealities in order to obtain accurate simulation results.
Consequently, we were able to address the significant challenges facing the high density memristor crossbar, as the building block for resistive-based memory systems and neural computing. For gateless arrays, we present multiport array structure and readout technique, which for the first time introduces a closed-form solution for the challenging crossbar sneak-paths problem. Moreover, a new adaptive threshold readout methodology is proposed, which employs the memory hierarchy locality property in order to improve the access time to the memristor crossbar. Another fast readout technique based on binary counters is presented for locality-less crossbar systems. On the other hand, for gated arrays, we present new readout technique and circuitry that combines the advantages of the gated and gateless memristor arrays, namely the high-density and low-power consumption. In general, the presented structures and readout methodologies empower much faster and power efficient access to the high-density memristive crossbar, compared to other works presented in the literature. Finally, at the circuit level, we propose novel reactance-less oscillators based on memristor devices, which find promising applications in embedded systems and bio-inspired computing. Altogether, we believe that our contributions to the emerging technology help to push it to the next level, shortening the path towards better futuristic computing systems.
|Date of Award||May 2015|
- Computer, Electrical and Mathematical Science and Engineering
|Supervisor||Khaled Salama (Supervisor)|