Variability and reliability in ultra-scaled MOS devices: How should they be evaluated from nanoscale to circuit level?

M. Nafría, R. Rodríguez, M. Porti, J. Martín-Martínez, M. Lanza, X. Aymerich

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Abstract

Intrinsic process variability and aging mechanisms will strongly affect circuit performance and reliability, so that they need to be considered during the design phase. In this paper, the approaches adopted at UAB to evaluate the nanoscale sources of device variability related to the MOSFETs gate oxide and to include device variability and aging during circuit simulation are described. First, the Conductive Atomic Force Microscope is used to evaluate the impact of processing on the morphological and electrical properties of the gate oxide at the nanoscale. As example, the impact of thermal annealing at different temperatures on the electrical properties of Al2O3/ SiO2 stacks is analyzed. Second, a reliability circuit simulation methodology, which combines Montecarlo and SPICE simulations, is presented to transfer the variability and aging effects in devices up to circuit level. The methodology is applied to evaluate the impact of threshold voltage time-dependent variability in differential amplifiers performance and reliability. ©The Electrochemical Society.
Original languageEnglish (US)
Title of host publicationECS Transactions
Pages225-236
Number of pages12
DOIs
StatePublished - Dec 30 2010
Externally publishedYes

ASJC Scopus subject areas

  • Engineering(all)

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