We study a group IV element: tin (Sn) by integrating it into silicon lattice, to enhance the performance of silicon CMOS. We have evaluated the electrical properties of the SiSn lattice by performing simulations using First-principle studies, followed by experimental device fabrication and characterization. We fabricated high-κ/metal gate based Metal-Oxide-Semiconductor capacitors (MOSCAPs) using SiSn as channel material to study the impact of Sn integration into silicon. © 2013 IEEE.
|Original language||English (US)|
|Title of host publication||2013 IEEE 8th Nanotechnology Materials and Devices Conference (NMDC)|
|Publisher||Institute of Electrical and Electronics Engineers (IEEE)|
|Number of pages||3|
|State||Published - Oct 2013|