Tin (Sn) for enhancing performance in silicon CMOS

Aftab M. Hussain, Hossain M. Fahad, Nirpendra Singh, Galo T. Sevilla, Udo Schwingenschlögl, Muhammad Mustafa Hussain

Research output: Chapter in Book/Report/Conference proceedingConference contribution

2 Scopus citations

Abstract

We study a group IV element: tin (Sn) by integrating it into silicon lattice, to enhance the performance of silicon CMOS. We have evaluated the electrical properties of the SiSn lattice by performing simulations using First-principle studies, followed by experimental device fabrication and characterization. We fabricated high-κ/metal gate based Metal-Oxide-Semiconductor capacitors (MOSCAPs) using SiSn as channel material to study the impact of Sn integration into silicon. © 2013 IEEE.
Original languageEnglish (US)
Title of host publication2013 IEEE 8th Nanotechnology Materials and Devices Conference (NMDC)
PublisherInstitute of Electrical and Electronics Engineers (IEEE)
Pages13-15
Number of pages3
ISBN (Print)9781479933877
DOIs
StatePublished - Oct 2013

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