With the onset of multi-core chips, the single-core market is closing down. Developing avionics systems hosted on multi-core chips that enforce safety-criticality constraints constitutes a challenge for the aerospace industry. This paper presents a reconfigurable multi-core architecture and studies its suitability for hosting safety-critical embedded applications. A task allocation algorithm for this specific architecture is proposed, and the last section demonstrates its behavior and analyzes its efficiency.
|Original language||English (US)|
|Title of host publication||AIAA/IEEE Digital Avionics Systems Conference - Proceedings|
|Publisher||Institute of Electrical and Electronics Engineers Inc.|
|State||Published - Nov 8 2017|