Systematic gate stack optimization to maximize mobility with HfSiON EOT scaling

M. A. Quevedo-Lopez, P. D. Kirsch, S. Krishnan, H. N. Alshareef, J. Barnett, H. R. Harris, A. Neugroschel, F. S. Aguirre-Tostado, B. E. Gnade, M. J. Kim, R. M. Wallace, B. H. Lee

Research output: Chapter in Book/Report/Conference proceedingConference contributionpeer-review

3 Scopus citations

Abstract

A systematic study to optimize gate stack constituents (interface, high- κ, metal gate) to maximize carrier mobility with aggressively scaled equivalent oxide thickness (EOT) is presented. We identify ultra-thin thermal oxide, atomic layer deposited HfSiON and optimized plasma nitridation performed in sequence as the optimized run path for sub-nm EOT scaling with high carrier mobility. A metal gate deposition process that minimizes the incorporation of impurities in HfSiON is also vital to maintaining good mobility at low EOTs.

Original languageEnglish (US)
Title of host publicationESSDERC 2006 - Proceedings of the 36th European Solid-State Device Research Conference
PublisherIEEE Computer Society
Pages113-116
Number of pages4
ISBN (Print)1424403014, 9781424403011
DOIs
StatePublished - Jan 1 2006
EventESSDERC 2006 - 36th European Solid-State Device Research Conference - Montreux, Switzerland
Duration: Sep 19 2006Sep 21 2006

Publication series

NameESSDERC 2006 - Proceedings of the 36th European Solid-State Device Research Conference
Volume2006-January

Other

OtherESSDERC 2006 - 36th European Solid-State Device Research Conference
CountrySwitzerland
CityMontreux
Period09/19/0609/21/06

ASJC Scopus subject areas

  • Electrical and Electronic Engineering
  • Electronic, Optical and Magnetic Materials

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