System simulation and optimization using reconfigurable hardware

Martin Lukasiewycz, Shanker Shreejith, Suhaib A. Fahmy

Research output: Chapter in Book/Report/Conference proceedingConference contribution

10 Scopus citations

Abstract

This paper presents a methodology for simulating and automatically optimizing distributed cyber-physical systems using reconfigurable hardware. By mapping an entire system of distributed devices including the buses onto a single Field Programmable Gate Array (FPGA), it becomes possible to make changes to the architecture, including the topology, using reconfiguration. This approach enables accurate rapid prototyping of distributed architectures, while also closing the gap between early simulation results and the final design, leading to a more robust optimization. Furthermore, the system can be simulated and optimized within a Hardware-in-the-Loop (HIL) setup due to its cycle-and bit-accurate execution in real-time. We introduce the general concept and building blocks that enable a faster and more accurate simulation and optimization: (1) The details of our approach for mapping devices, network interfaces, and buses onto an FPGA are presented. (2) An optimization model is proposed that encodes the topology, task distribution, and communication in a very efficient representation. Finally, the implementation and integration of the methodology is presented and discussed.
Original languageEnglish (US)
Title of host publicationProceedings of the 14th International Symposium on Integrated Circuits, ISIC 2014
PublisherInstitute of Electrical and Electronics Engineers Inc.
Pages468-471
Number of pages4
ISBN (Print)9781479948338
DOIs
StatePublished - Feb 2 2015
Externally publishedYes

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