Strain-enhanced scaling of HK+MG CMOSFETs

S. C. Song*, M. M. Hussain, C. Burham, C. S. Park, B. H. Lee, R. Jammy

*Corresponding author for this work

Research output: Contribution to journalArticlepeer-review

Abstract

Recent advancement in high-k and metal gate (HK+MG) technology has allowed improvements in gate control owing to the aggressive scaling of equivalent oxide thickness (EOT), which has not been possible with conventional SiO 2/poly-gate technology. To continue to scale CMOS devices and get the full benefit of HK+MG technology, it is important to study how process-induced strain (PIS) interferes with the high-k/metal gate and how the new process should be used to generate an additional source of PIS. This article will describe recent data on the effects of metal gate-induced strain on MOSFET performance and interactions with the conventional PIS technique.

Original languageEnglish (US)
Pages (from-to)46-49
Number of pages4
JournalSolid State Technology
Volume50
Issue number9
StatePublished - Sep 2007
Externally publishedYes

ASJC Scopus subject areas

  • Electronic, Optical and Magnetic Materials
  • Condensed Matter Physics
  • Materials Chemistry
  • Electrical and Electronic Engineering

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