Strain engineering in nanoscale CMOS FinFETs and methods to optimize R S/D

Casey Smith*, Srivatsan Parthasarathy, Brian E. Coss, Jason Williams, Hemant Adhikari, Greg Smith, Barry Sassman, Muhammad Mustafa Hussain, Prashant Majhi, Raj Jammy

*Corresponding author for this work

Research output: Chapter in Book/Report/Conference proceedingConference contributionpeer-review

6 Scopus citations

Abstract

For the first time, we demonstrate stressor contact etch stop liner (sCESL) modulation of parasitics/external resistance in nonplanar devices. We report 17% saturation drive current enhancement in underlap doped cMOS FinFETs attributed to simultaneous lowering of RS/D via biaxial S/D stress and μo increase via effective uniaxial channel stress. Our observations imply that biaxial strain engineering for reduction of R S/D offers a significant opportunity to realize non-planar CMOSFET performance metrics for the 22nm node and beyond.

Original languageEnglish (US)
Title of host publicationProceedings of 2010 International Symposium on VLSI Technology, System and Application, VLSI-TSA 2010
Pages156-157
Number of pages2
DOIs
StatePublished - Oct 20 2010
Event2010 International Symposium on VLSI Technology, System and Application, VLSI-TSA 2010 - Hsin Chu, Taiwan, Province of China
Duration: Apr 26 2010Apr 28 2010

Publication series

NameProceedings of 2010 International Symposium on VLSI Technology, System and Application, VLSI-TSA 2010

Other

Other2010 International Symposium on VLSI Technology, System and Application, VLSI-TSA 2010
CountryTaiwan, Province of China
CityHsin Chu
Period04/26/1004/28/10

Keywords

  • Biaxial stress
  • CESL
  • FinFET
  • R
  • Stressor

ASJC Scopus subject areas

  • Computer Networks and Communications
  • Hardware and Architecture

Fingerprint

Dive into the research topics of 'Strain engineering in nanoscale CMOS FinFETs and methods to optimize R <sub>S/D</sub>'. Together they form a unique fingerprint.

Cite this