Slow trap charging and detrapping in the negative bias temperature instability in HfSiON dielectric based field effect transistors

R. A.B. Devine, Husam Niman Alshareef, M. A. Quevedo-Lopez

Research output: Contribution to journalArticlepeer-review

3 Scopus citations

Abstract

Negative bias temperature instability in HfSiON gate dielectric based p -channel transistors has been studied at 293, 363, 398, and 433 K and the "slow trap" creation and relaxation has been investigated. Analysis of transistor characteristics suggests that slow trapping in this case is almost entirely related to positive charge trapping in the dielectric as opposed to the dielectric/semiconductor interface. A linear threshold voltage shift versus fractional mobility variation relationship is established as expected. A simplified approach is used to crudely estimate the importance of fast relaxing trapped charges and its magnitude estimated for the four temperatures studied in this work.

Original languageEnglish (US)
Article number124109
JournalJournal of Applied Physics
Volume104
Issue number12
DOIs
StatePublished - Dec 1 2008

ASJC Scopus subject areas

  • Physics and Astronomy(all)

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