RPN oxynitride gate dielectrics for 90nm low power CMOS applications

A. Veloso*, M. Jurczak, F. N. Cubaynes, R. Rooyackers, S. Mertens, A. Rothschild, M. Schaekers, H. N. Al-Shareef, R. W. Murto, C. J J Dachs, G. Badenes

*Corresponding author for this work

Research output: Chapter in Book/Report/Conference proceedingConference contributionpeer-review

8 Scopus citations

Abstract

This paper investigates the use of RPN-based oxynitride gate dielectrics for 90 nm Low Power (LP) CMOS applications. Several recipes have been developed to optimise the gate dielectric for targeted EOT, high mobility and improved EOT uniformity. Compared to conventional furnace oxynitride, significant gate leakage reduction has been found in devices with plasma nitrided oxides. This enabled reaching the spec for the IOFF current of 20 pA/μm and improve the ION-IOFF trade-off. The ION current obtained at 1.2 V for NMOS and PMOS devices is 427 μA/μm (at IOFF =16 pA/μm) and 170 μA/μm (at IOFF =16 pA/μm), respectively. The obtained results are among the best values reported in the literature.

Original languageEnglish (US)
Title of host publicationEuropean Solid-State Device Research Conference
PublisherIEEE Computer Society
Pages159-162
Number of pages4
ISBN (Electronic)8890084782
DOIs
StatePublished - 2002
Externally publishedYes
Event32nd European Solid-State Device Research Conference, ESSDERC 2002 - Firenze, Italy
Duration: Sep 24 2002Sep 26 2002

Other

Other32nd European Solid-State Device Research Conference, ESSDERC 2002
CountryItaly
CityFirenze
Period09/24/0209/26/02

ASJC Scopus subject areas

  • Electrical and Electronic Engineering
  • Safety, Risk, Reliability and Quality

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