Resizable data composer (RDC) cache: A near-threshold cache tolerating process variation via architectural fault tolerance

Avesta Sasan, Fadi J. Kurhadi, Ahmed M. Eltawil

Research output: Chapter in Book/Report/Conference proceedingChapter

Abstract

In this chapter a novel fault tolerant cache architecture named Resizable Data Composer-Cache (RDC-Cache) is introduced. This configurable cache architecture is custom designed to operate correctly in Near-Threshold voltages, at sub 500 mV in 65 nm technology while tolerating a large number of Manufacturing Process Variation induced defects. Based on a smart relocation and resizing methodology, RDC-Cache decomposes the data that is targeted for a defective cache way and relocates one or more data words to a new location avoiding a write to defective bit locations. When servicing a read request, the requested data is reconstructed through an inverse operation. For the purpose of fault tolerance at low voltages the cache size is reduced, however, in this architecture the final cache size is considerably higher compared to previously suggested resizable cache organizations (Agarwal et al., Trans Solid State Circuits 40(9), 2005; Wilkerson et al., ISCA, 2008). The following three features (a) compaction of relocated words, (b) ability to use defective words for fault tolerance and (c) “linking” (relocating the defective word to any row in the next bank), allows this architecture to achieve far larger fault tolerance in comparison to Agarwal et al. (Trans Solid State Circuits 40(9)) and Wilkerson et al. (ISCA, 2008). In high voltage mode, the fault tolerant mechanism of RDC-Cache is turned-off with minimal (0.91 %) latency overhead compared to a traditional cache.
Original languageEnglish (US)
Title of host publicationNear Threshold Computing: Technology, Methods and Applications
PublisherSpringer International Publishing
ISBN (Print)9783319233895
DOIs
StatePublished - Jan 1 2015
Externally publishedYes

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