In this paper, a compact architecture and implementation for direct digital frequency synthesis (DDFS) is presented. It uses a smaller lookup table for sinusoidal functions compared to existing architectures. The computation of the sinusoidal values is performed by a parabolic interpolation structure, thus only interpolation coefficients need to be stored in the Read-Only Memory (ROM). The ROM size is consistently less than 1 Kbits for SFDR values up to 85 dBc.
|Original language||English (US)|
|Title of host publication||Proceedings of the Custom Integrated Circuits Conference|
|State||Published - Jan 1 2002|