Performance Limits and Potential of Multilayer Graphene–Tungsten Diselenide Heterostructures

Shih-Hsien Yang, Feng-Shou Yang, Hao-Ling Tang, Ming-Hui Chiu, Ko-Chun Lee, Mengjiao Li, Che-Yi Lin, Lain-Jong Li, Vincent Tung, Yong Xu, Yumeng Shi, Chen-Hsin Lien, Yen-Fu Lin

Research output: Contribution to journalArticlepeer-review

Abstract

Atomically thin tungsten diselenide (WSe2) transistors with multilayer graphene (w/ G) as contact electrodes are successfully fabricated by a precise area-controllable chemical vapor deposition method. The performance and electrical properties of the devices are explored. Compared to those of WSe2 transistors without graphene contacts (w/o G), the maximum current densities of the w/ G–WSe2 transistors increase by one to two orders of magnitude. In addition, the device performance is markedly improved for the w/ G–WSe2 transistors, including an on/off current ratio of ≈107, subthreshold swing of ≈150 mV/decade, and threshold voltage of ≈1.75 V. The improved performance of the w/ G–WSe2 transistors is ascribed to the alleviation of electrical contributions from metal–semiconductor contact resistance, which is consistent with the analysis of low-frequency noise measurements. In addition, self-trapping behavior in the WSe2 channel is found, which possibly paves a way to further optimize the performance of layered devices. Finally, an inverter using the w/ G–WSe2 transistors is demonstrated. These transistors represent a step forward in the development of layered graphene-based electronics suitable for energy-efficient and high-performance industrial-scale products.
Original languageEnglish (US)
Pages (from-to)2100355
JournalAdvanced Electronic Materials
DOIs
StatePublished - Sep 2 2021

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