Optimization Techniques for Dimensionally Truncated Sparse Grids on Heterogeneous Systems

A. Deftu, A. Murarasu

Research output: Chapter in Book/Report/Conference proceedingConference contribution

3 Scopus citations

Abstract

Given the existing heterogeneous processor landscape dominated by CPUs and GPUs, topics such as programming productivity and performance portability have become increasingly important. In this context, an important question refers to how can we develop optimization strategies that cover both CPUs and GPUs. We answer this for fastsg, a library that provides functionality for handling efficiently high-dimensional functions. As it can be employed for compressing and decompressing large-scale simulation data, it finds itself at the core of a computational steering application which serves us as test case. We describe our experience with implementing fastsg's time critical routines for Intel CPUs and Nvidia Fermi GPUs. We show the differences and especially the similarities between our optimization strategies for the two architectures. With regard to our test case for which achieving high speedups is a "must" for real-time visualization, we report a speedup of up to 6.2x times compared to the state-of-the-art implementation of the sparse grid technique for GPUs. © 2013 IEEE.
Original languageEnglish (US)
Title of host publication2013 21st Euromicro International Conference on Parallel, Distributed, and Network-Based Processing
PublisherInstitute of Electrical and Electronics Engineers (IEEE)
Pages351-358
Number of pages8
ISBN (Print)9781467353212
DOIs
StatePublished - Feb 2013
Externally publishedYes

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