This paper presents a digital implementation of a 3rd order chaotic system using the Euler approximation. Short-term predictability is studied in relation to system precision, Euler step size and attractor size and optimal parameters for maximum performance are derived. Defective bits from the native chaotic output are neglected and the remaining pass the NIST SP. 800-22 tests without post-processing. The resulting optimized pseudorandom number generator has throughput up to 17.60 Gbits/s for a 64-bit design experimentally verified on a Xilinx Virtex 4 FPGA with logic utilization less than 1.85%.
|Original language||English (US)|
|Title of host publication||2013 IEEE 20th International Conference on Electronics, Circuits, and Systems (ICECS)|
|Publisher||Institute of Electrical and Electronics Engineers (IEEE)|
|Number of pages||4|
|State||Published - May 16 2014|