An efficient hardware implementation of a median filter is presented. Input samples are used to construct a cumulative histogram, which is then used to find the median. The resource usage of the design is independent of window size, but rather, dependent on the number of bits in each input sample. This offers a realisable way of efficiently implementing large-windowed median filtering, as required by transforms such as the Trace Transform. The method is then extended to weighted median filtering. The designs are synthesised for a Xilinx Virtex II FPGA and the performance and area compared to another implementation for different sized windows. Intentional use of the heterogeneous resources on the FPGA in the design allows for a reduction in slice usage, and high throughput. © 2005 IEEE.
|Original language||English (US)|
|Title of host publication||Proceedings - 2005 International Conference on Field Programmable Logic and Applications, FPL|
|Number of pages||6|
|State||Published - Dec 1 2005|