The design of efficient multiprocessor systems on chip (MPSoC) is a daunting challenge. This challenge is driven by the increasing demand in achieving high performance, low power, and reconfigurable applications onto the same platform. As a consequence, there is an emerging need for fast, and efficient design space exploration, while providing abstract models for a wide range of applications, and types of processing units (PUs). Therefore, this paper proposes a framework for a fast MPSoC generation with joint task and core mapping with the objective of minimizing the average power consumption. The proposed framework considers the static, dynamic, reconfiguration and communication power components. A tool for high level MPSoC task and core mapping (MPMAP) is built based on the proposed framework. MPMAP provides a flexible XML interface that provides a high level description of the different PU architectures, and different applications scenarios. Additionally, the paper presents a case study of real-life applications that can be adopted in future heterogeneous wireless systems. © 2013 IEEE.