Microkernel hypervisor for a hybrid ARM-FPGA platform

Khoa Dang Pham, Abhishek Kumar Jain, Jin Cui, Suhaib A. Fahmy, Douglas L. Maskell

Research output: Chapter in Book/Report/Conference proceedingConference contribution

16 Scopus citations

Abstract

Reconfigurable architectures have found use in a wide range of application domains, but mostly as static accelerators for computationally intensive functions. Commodity computing adoption has not taken off due primarily to design complexity challenges. Yet reconfigurable architectures offer significant advantages in terms of sharing hardware between distinct isolated tasks, under tight time constraints. Trends towards amalgamation of computing resources in the automotive and aviation domains have so far been limited to non-critical systems, because processor approaches suffer from a lack of predictability and isolation. Hybrid reconfigurable platforms may provide a promising solution to this, by allowing physically isolated access to hardware resources, and support for computationally demanding applications, but with improved programmability and management. We propose virtualized execution and management of software and hardware tasks using a microkernel-based hypervisor running on a commercial hybrid computing platform (the Xilinx Zynq). We demonstrate a framework based on the CODEZERO hypervisor, which has been modified to leverage the capabilities of the FPGA fabric. It supports discrete hardware accelerators, dynamically reconfigurable regions, and regions of virtual fabric, allowing for application isolation and simpler use of hardware resources. A case study demonstrating multiple independent (and isolated) software and hardware tasks is presented. © 2013 IEEE.
Original languageEnglish (US)
Title of host publicationProceedings of the International Conference on Application-Specific Systems, Architectures and Processors
Pages219-226
Number of pages8
DOIs
StatePublished - Sep 9 2013
Externally publishedYes

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