Method and system for address trace compression through loop detection and reduction

Research output: Patent

Abstract

A method and system for compressing memory address traces based on detecting and reducing the loops that exist in a trace is disclosed. The method and system consists of two steps. In the first step, the trace is analyzed and loops are detected by determining the control flow among the program basic blocks. In the second step, each loop is analyzed to eliminate constant address references, and to apply compiler-like strength reduction on addresses that differ only by a fixed offset between consecutive loop iterations. Addresses that cannot be eliminated using the method and system of the present invention are kept in the trace.

Original languageEnglish (US)
Patent numberUS6347383
IPCG06F 11/ 36 A I
Priority date03/31/99
StatePublished - Feb 12 2002
Externally publishedYes

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