Mapping for maximum performance on FPGA DSP blocks

Bajaj Ronak, Suhaib A. Fahmy

Research output: Contribution to journalArticlepeer-review

23 Scopus citations

Abstract

The digital signal processing (DSP) blocks on modern field programmable gate arrays (FPGAs) are highly capable and support a variety of different datapath configurations. Unfortunately, inference in synthesis tools can fail to result in circuits that reach maximum DSP block throughput. We have developed a tool that maps graphs of add/sub/mult nodes to DSP blocks on Xilinx FPGAs, ensuring maximum throughput. This is done by delaying scheduling until after the graph has been partitioned onto DSP blocks and scheduled based on their pipeline structure, resulting in a throughput optimized implementation. Our tool prepares equivalent implementations in a variety of other methods, including high-level synthesis (HLS) for comparison. We show that the proposed approach offers an improvement in frequency of 100% over standard pipelined code, and 23% over Vivado HLS synthesis implementation, while retaining code portability, at the cost of a modest increase in logic resource usage.
Original languageEnglish (US)
Pages (from-to)573-585
Number of pages13
JournalIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Volume35
Issue number4
DOIs
StatePublished - Apr 1 2016
Externally publishedYes

ASJC Scopus subject areas

  • Computer Graphics and Computer-Aided Design
  • Software
  • Electrical and Electronic Engineering

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