Approximate computing helps achieve better performance or energy efficiency by trading accuracy. Most approximate adders are composed of multiple sub-adders and long carry chains are split to reduce latency, thus benefiting from the fact that carry propagation across long carry chains is rare for uniformly distributed inputs. One key tradeoff of these approximate adders is between latency and error rate. The more prediction bits are used, the lower is the error rate, but the latency is longer. In this paper, we present a Correlation Aware Predictor (CAP) which utilizes spatial-temporal correlation information of input streams to predict carry-in value for sub-adders. CAP uses less prediction bits which help reduce adder latency significantly. For highly correlated input streams, we found that CAP can reduce adder latency by about 23% at the same error rate compared to prior work. We implemented a CAP-based approximate adder in Verilog and synthesized with TSMC 16nm library. Synthesis results show that CAP-based adder can reduce latency by 25% and save 13% in silicon area compared to state-of-the-art.
|Original language||English (US)|
|Title of host publication||Proceedings - 35th IEEE International Conference on Computer Design, ICCD 2017|
|Publisher||Institute of Electrical and Electronics Engineers Inc.|
|State||Published - Nov 22 2017|