This paper proposes a new low power cache architecture that utilizes fault tolerance to allow aggressively reduced voltage levels. The fault tolerant overhead circuits consume little energy, but enable the system to operate correctly and boost the system performance to close to defect free operation. Overall, power savings of over 40% are reported on standard benchmarks. © 2007 IEEE.
|Original language||English (US)|
|Title of host publication||2007 IEEE International Conference on Computer Design, ICCD 2007|
|State||Published - Dec 1 2007|