Lightweight programmable DSP block overlay for streaming neural network acceleration

Lenos Ioannou, Suhaib A. Fahmy

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Abstract

Implementations of hardware accelerators for neural networks are increasingly popular on FPGAs, due to flexibility, achievable performance and efficiency gains resulting from network optimisations. The long compilation time required by the backend toolflow, however, makes rapid deployment and prototyping of such accelerators on FPGAs more difficult. Moreover, achieving high frequency of operation requires significant low-level design effort. We present a neural network overlay for FPGAs that exploits DSP blocks, operating at near their theoretical maximum frequency, while minimizing resource utilization. The proposed architecture is flexible, enabling rapid runtime configuration of network parameters according to the desired network topology. It is tailored for lightweight edge implementations requiring acceleration, rather than the highest throughput achieved by more complex architectures in the datacenter.
Original languageEnglish (US)
Title of host publicationProceedings - 2019 International Conference on Field-Programmable Technology, ICFPT 2019
PublisherInstitute of Electrical and Electronics Engineers Inc.
Pages355-358
Number of pages4
ISBN (Print)9781728129433
DOIs
StatePublished - Dec 1 2019
Externally publishedYes

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