La-doped metal/high-K nMOSFET for sub-32nm HP and LSTP application

C. S. Park, J. W. Yang, Muhammad Mustafa Hussain, C. Y. Kang, J. Huang, P. Sivasubramani, C. Park, K. Tateiwa, Y. Harada, J. Barnett, C. Melvin, G. Bersuker, P. D. Kirsch, B. H. Lee, H. H. Tseng, R. Jammy

Research output: Chapter in Book/Report/Conference proceedingConference contributionpeer-review

2 Scopus citations

Abstract

This paper presents results on nMOSFETs with the La-doped high-k/metal gate stack to see its suitability for sub-32nm LSTP and HP applications. The 32nm gate length transistors exhibit an excellent Ion-Ioff characteristic, and the PBTI results meet the 32nm technology node requirement. Furthermore, for the first time, Vt variation in the La-doped high-k/metal gate stack devices is investigated. The results suggest that employing the metal electrode suppresses Vt variability while no additional parameter fluctuations due to La-doping of the high-k dielectric were observed.

Original languageEnglish (US)
Title of host publication2009 International Symposium on VLSI Technology, Systems, and Applications, VLSI-TSA '09
Pages59-60
Number of pages2
DOIs
StatePublished - Dec 1 2009
Event2009 International Symposium on VLSI Technology, Systems, and Applications, VLSI-TSA '09 - Hsinchu, Taiwan, Province of China
Duration: Apr 27 2009Apr 29 2009

Publication series

NameInternational Symposium on VLSI Technology, Systems, and Applications, Proceedings

Other

Other2009 International Symposium on VLSI Technology, Systems, and Applications, VLSI-TSA '09
CountryTaiwan, Province of China
CityHsinchu
Period04/27/0904/29/09

ASJC Scopus subject areas

  • Electronic, Optical and Magnetic Materials
  • Condensed Matter Physics
  • Electrical and Electronic Engineering

Fingerprint Dive into the research topics of 'La-doped metal/high-K nMOSFET for sub-32nm HP and LSTP application'. Together they form a unique fingerprint.

Cite this