Investigation on the mechanism of the leakage failure between poly gate and contact in subnano technology

Q. F. Wang, S. L. Toh, Q. Deng, P. K. Tan, Kun Li, J. Teong, Z. H. Mai, J. Lam

Research output: Chapter in Book/Report/Conference proceedingConference contributionpeer-review

1 Scopus citations

Abstract

With the shrinkage of the transistor dimensions, the spacing between the structures become smaller and smaller. However due to the intrinsic characteristic of the CMOS device, the reduction of the operating voltage is limited. The electrical field between different structures keeps on increasing with the shrinkage of the transistor dimensions. Furthermore, many new failure modes were observed with the scaling of semiconductor device. One of them is poly gate to contact leakage. In this paper, the mechanism of the leakage failure between poly gate and the contact in subnano CMOS technology was discussed.

Original languageEnglish (US)
Title of host publication2008 15th IEEE International Symposium on the Physical and Failure Analysis of Integrated Circuits, IPFA
DOIs
StatePublished - Sep 23 2008
Event2008 15th IEEE International Symposium on the Physical and Failure Analysis of Integrated Circuits, IPFA - Singapore, Singapore
Duration: Jul 7 2008Jul 11 2008

Publication series

NameProceedings of the International Symposium on the Physical and Failure Analysis of Integrated Circuits, IPFA

Other

Other2008 15th IEEE International Symposium on the Physical and Failure Analysis of Integrated Circuits, IPFA
CountrySingapore
CitySingapore
Period07/7/0807/11/08

ASJC Scopus subject areas

  • Engineering(all)

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