Interpolation based direct digital frequency synthesis for wireless communications

Ahmed M. Eltawil, Babak Daneshrad

Research output: Chapter in Book/Report/Conference proceedingConference contribution

14 Scopus citations

Abstract

In this paper, a compact architecture for direct digital frequency synthesis (DDFS) is presented. It uses a smaller lookup table for sine and cosine functions compared to existing architectures, with minimal hardware overhead. The computation of the sinusoidal values is performed by a parabolic interpolation structure, thus only interpolation coefficients need to be stored in the read-only memory (ROM). A DDFS with 64 dBc SFDR, 10-bit output resolution and 32 bit phase accumulator requires only 104 bits of ROM storage. The ROM size is consistently less than 1 Kbits for SFDR up to 85 dBc.
Original languageEnglish (US)
Title of host publicationIEEE Wireless Communications and Networking Conference, WCNC
PublisherInstitute of Electrical and Electronics Engineers Inc.
ISBN (Print)0780373766
DOIs
StatePublished - Jan 1 2002
Externally publishedYes

Fingerprint Dive into the research topics of 'Interpolation based direct digital frequency synthesis for wireless communications'. Together they form a unique fingerprint.

Cite this