Integration of a poisoning-free dual damascene CDO film stack for 90 nm & beyond low-k BEOL

Wu Ping Liu*, Juan Boon Tan, Wei Lu, Shyam Pal, Yong Kong Siew, Hai Cong, Bei Chao Zhang, Xianbin Wang, Fan Zhang, Liang Choo Hsia

*Corresponding author for this work

    Research output: Chapter in Book/Report/Conference proceedingConference contributionpeer-review

    Abstract

    In this paper we report on the successful integration of a 90nm low-k full VIA-first dual damascene process architecture using carbon-doped-oxide (CDO) and SiC etch-stop-layer (ESL). One of the key features of the integration scheme is that the effects of photoresist poisoning have been eliminated by optimization of the low-k (k< 3.0) film stack deposition process. The mechanisms underlying photoresist poisoning have been investigated through detailed partition studies. Electrical yield and reliability data will be shown to demonstrate the performance of the overall integration approach.

    Original languageEnglish (US)
    Title of host publication2005 IEEE VLSI-TSA - International Symposium on VLSI Technology - VLSI-TSA - TECH, Proceedings of Technical Papers
    Pages70-71
    Number of pages2
    StatePublished - Oct 31 2005
    Event2005 IEEE VLSI-TSA - International Symposium on VLSI Technology - VLSI-TSA-TECH - Hsinchu, Taiwan, Province of China
    Duration: Apr 25 2005Apr 27 2005

    Publication series

    Name2005 IEEE VLSI-TSA - International Symposium on VLSI Technology - VLSI-TSA-TECH, Proceedings of Technical Papers

    Other

    Other2005 IEEE VLSI-TSA - International Symposium on VLSI Technology - VLSI-TSA-TECH
    CountryTaiwan, Province of China
    CityHsinchu
    Period04/25/0504/27/05

    ASJC Scopus subject areas

    • Engineering(all)

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