Integration challenges and opportunities for nanometer scale dual metal gate CMOSFET

S. C. Song, Muhammad Mustafa Hussain, J. Barnett, C. S. Park, C. Park, P. Kirsch, B. H. Lee, R. Jammy

Research output: Chapter in Book/Report/Conference proceedingConference contributionpeer-review

3 Scopus citations

Abstract

As MOSFET scales below 45nm, conventional SiO2 cannot sustain equivalent oxide thickness (EOT) and leakage current requirements set in the International Technology Roadmap for Semiconductors (ITRS), due to the limitation of physical-thickness scaling, and high tunneling current [1]. Metal gate and high-k dielectric have been extensively studied to overcome the limitation of conventional poly gate and SiO2 technology. Although recent advancements of the technology enable the metal gate and high-k dielectric to be implemented in actual manufacturing, several issues remain associated with integrating the new materials in CMOS field-effect transistors (FETs). This paper will introduce various integration schemes for fabricating dual metal gate CMOSFET, and review pros and cons of each approach to propose general integration guide for the desired application.

Original languageEnglish (US)
Title of host publicationECS Transactions - 5th International Symposium on ULSI Process Integration
Pages315-329
Number of pages15
Edition6
DOIs
StatePublished - Dec 1 2007
Event5th International Symposium on ULSI Process Integration - 212th ECS Meeting - Washington, DC, United States
Duration: Oct 7 2007Oct 12 2007

Publication series

NameECS Transactions
Number6
Volume11
ISSN (Print)1938-5862
ISSN (Electronic)1938-6737

Other

Other5th International Symposium on ULSI Process Integration - 212th ECS Meeting
CountryUnited States
CityWashington, DC
Period10/7/0710/12/07

ASJC Scopus subject areas

  • Engineering(all)

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