Improved StrongARM latch comparator: Design, analysis and performance evaluation

Abdullah Saud Mohammed Almansouri, Abdullah Turki Al-Turki, Abdullah Alshehri, Talal Al Attar, Talal Al Attar, Hossein Fariborzi

    Research output: Chapter in Book/Report/Conference proceedingConference contribution

    6 Scopus citations

    Abstract

    This paper presents an improved StrongARM latch comparator, designed and simulated in 90nm and 32nm CMOS technologies. The proposed design provides an improvement of 7% in energy efficiency, 14% in speed and an average reduction of 41% in the clock feedthrough, compared to the conventional design. The new architecture also minimizes the area by reducing the required transistors needed for the enhanced performance.
    Original languageEnglish (US)
    Title of host publication2017 13th Conference on Ph.D. Research in Microelectronics and Electronics (PRIME)
    PublisherInstitute of Electrical and Electronics Engineers (IEEE)
    Pages89-92
    Number of pages4
    ISBN (Print)9781509065080
    DOIs
    StatePublished - Jul 13 2017

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