Hotspot detection and design recommendation using silicon calibrated CMP model

Colin Hui*, Xianbin Wang, Haigou Huang, Ushasree Katakamsetty, Laertis Economikos, Mohammed Fayaz, Stephen Greco, Hua Xiang, Subramanian Jayathi, Yuan Chi-Min, Li Song, Vikas Mehrotra, Kuang Han Chen, Tamba Gbondo-Tugbawa, Taber Smith

*Corresponding author for this work

    Research output: Chapter in Book/Report/Conference proceedingConference contributionpeer-review

    14 Scopus citations

    Abstract

    Chemical Mechanical Polishing (CMP) has been used in the manufacturing process for copper (Cu) damascene process. It is well known that dishing and erosion occur during CMP process, and they strongly depend on metal density and line width. The inherent thickness and topography variations become an increasing concern for today's designs running through advanced process nodes (sub 65nm). Excessive thickness and topography variations can have major impacts on chip yield and performance; as such they need to be accounted for during the design stage. In this paper, we will demonstrate an accurate physics based CMP model and its application for CMP-related hotspotdetection. Model based checking capability is most useful to identify highly environment sensitive layouts that are prone to early process window limitation and hence failure. Model based checking as opposed to rule based checking can identify more accurately the weak points in a design and enable designers to provide improved layout for the areas with highest leverage for manufacturability improvement. Further, CMP modeling has the ability to provide information on interlevel effects such as copper puddling from underlying topography that cannot be captured in Design-for- Manufacturing (DfM) recommended rules. The model has been calibrated against the silicon produced with the 45nm process from Common Platform (IBMChartered- Samsung) technology. It is one of the earliest 45nm CMP models available today. We will show that the CMP-related hotspots can often occur around the spaces between analog macros and digital blocks in the SoC designs. With the help of the CMP model-based prediction, the design, the dummy fill or the placement of the blocks can be modified to improve planarity and eliminate CMP-related hotspots. The CMP model can be used to pass design recommendations to designers to improve chip yield and performance.

    Original languageEnglish (US)
    Title of host publicationDesign for Manufacturability through Design-Process Integration III
    DOIs
    StatePublished - Jun 15 2009
    EventDesign for Manufacturability through Design-Process Integration III - San Jose, CA, United States
    Duration: Feb 26 2009Feb 27 2009

    Publication series

    NameProceedings of SPIE - The International Society for Optical Engineering
    Volume7275
    ISSN (Print)0277-786X

    Other

    OtherDesign for Manufacturability through Design-Process Integration III
    CountryUnited States
    CitySan Jose, CA
    Period02/26/0902/27/09

    Keywords

    • Chemical mechanical polishing (CMP)
    • Copper puddling
    • Design for manufacturability (DFM)
    • Topography

    ASJC Scopus subject areas

    • Electronic, Optical and Magnetic Materials
    • Condensed Matter Physics
    • Computer Science Applications
    • Applied Mathematics
    • Electrical and Electronic Engineering

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