Process variability and energy consumption are the two most formidable challenges facing the semiconductor industry nowadays. To combat these challenges, we present in this paper the "History and Variation Trained-Cache" (HVT-Cache) architecture. HVT-Cache enables fine grain voltage scaling within a memory bank by taking into account both memory access pattern and process variability. The supply voltage is changed with alterations in the memory access pattern to maximize power saving, while assuring safe operation (read and write) by guarding against process variability. In a case study, SimpleScalar simulation of the proposed 32KB cache architecture reports over 40% reduction in power consumption over standard SPEC2000 integer benchmarks while incurring an area overhead below 4% and an execution time penalty smaller than 1%. © 2012 IEEE.
|Original language||English (US)|
|Title of host publication||Proceedings - International Symposium on Quality Electronic Design, ISQED|
|State||Published - Jul 16 2012|