Highly manufacturaba 45nm LSTP CMOSFETs using novel dual high-k and dual metal gate CMOS integration

S. C. Song, Z. B. Zhang, Muhammad Mustafa Hussain, C. Huffman, J. Barnett, S. H. Bae, H. J. Li, P. Majhi, C. S. Park, B. S. Ju, H. K. Park, C. Y. Kang, R. Choi, P. Zeitzoff, H. H. Tseng, B. H. Lee, R. Jammy

Research output: Chapter in Book/Report/Conference proceedingConference contributionpeer-review

41 Scopus citations

Abstract

This paper reports the first demonstration of dual high-k and dual metal gate (DHDMG) CMOSFETs meeting the device targets of 45nm low stand-by power (LSTP) node. This novel scheme has several advantages over the previously reported dual metal gate integration, enabling the high-k and metal gate processes to be optimized separately for N and PMOSFETs in order to maximize performance gain and process controllability. The proposed gate stack integration results in a symmetric short channel Vt of ∼±0.45V with >80% high field mobility for both N and PMOSFETs and significantly lower gate leakage compared to poly/SiON stack.

Original languageEnglish (US)
Title of host publication2006 Symposium on VLSI Technology, VLSIT - Digest of Technical Papers
Pages13-14
Number of pages2
StatePublished - Dec 1 2006
Event2006 Symposium on VLSI Technology, VLSIT - Honolulu, HI, United States
Duration: Jun 13 2006Jun 15 2006

Publication series

NameDigest of Technical Papers - Symposium on VLSI Technology
ISSN (Print)0743-1562

Other

Other2006 Symposium on VLSI Technology, VLSIT
CountryUnited States
CityHonolulu, HI
Period06/13/0606/15/06

ASJC Scopus subject areas

  • Electrical and Electronic Engineering

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