High-Performance Vertical Gate-All-Around Silicon Nanowire FET With High-kappa/Metal Gate

Yujia Zhai, Leo Mathew, Rajesh Rao, Marylene Palard, Sonali Chopra, John G. Ekerdt, Leonard F. Register, Sanjay K. Banerjee

Research output: Contribution to journalArticlepeer-review

15 Scopus citations

Abstract

We present a vertical gate-all-around Si nanowire (SiNW) metal-oxide-semiconductor field-effect transistor with high-κ dielectric and TiN metal gate. The process flow is fully compatible with CMOS technologies. SiNWs are fabricated by deep Si reactive ion etching, gate-stack is formed by atomic layer deposition, and metal salicide is utilized as drain contact. The fabricated p-type gate-all-around SiNW metal-oxide-semiconductor field-effect transistors that have a gate length of 320 nm exhibit excellent characteristics with ION/IOFF > 104, subthreshold slope of 87 mV/decade, and 25 mV/V of drain-induced barrier lowering. Low-temperature characteristics are also presented. The demonstrated devices have potential applications in novel low-power logic circuits and as selection transistors for 4F2 cross-point memory cells.
Original languageEnglish (US)
Pages (from-to)3896-3900
Number of pages5
JournalIEEE TRANSACTIONS ON ELECTRON DEVICES
Volume61
Issue number11
DOIs
StatePublished - 2014
Externally publishedYes

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