Gate first high-k/metal gate stacks with zero SiO x interface achieving EOT=0.59nm for 16nm application

J. Huang*, D. Heh, P. Sivasubramani, P. D. Kirsch, G. Bersuker, D. C. Gilmer, M. A. Quevedo-Lopez, Muhammad Mustafa Hussain, P. Majhi, P. Lysaght, H. Park, N. Goel, C. Young, C. S. Park, C. Park, M. Cruz, V. Diaz, P. Y. Hung, J. Price, H. H. TsengR. Jammy

*Corresponding author for this work

Research output: Chapter in Book/Report/Conference proceedingConference contributionpeer-review

47 Scopus citations

Abstract

Gate first 0.59nm EOT HfO x /metal gate stacks for 16 nm node application are demonstrated for the first time. By controlling O during HfO x deposition, "zero" low-k SiO x interface (ZIL) forms despite a 1020oC activation anneal. This 0.59nm EOT is a 30% improvement over a state of the art 32nm HK/MG technology [1]. We compare and demonstrate for the first time the improved scalability of ZIL HfO x vs. exotic higher-k. Transistors made with ZIL HfO x show good interfaces (SS=70-80 mV/dec, N it =5×10 10 /cm 2 ) and performance (10% I on -I off boost vs. EOT=0.95nm), despite mobility loss. Factors contributing to mobility loss in ZIL HfO x are discussed.

Original languageEnglish (US)
Title of host publication2009 Symposium on VLSI Technology, VLSIT 2009
Pages34-35
Number of pages2
StatePublished - Nov 16 2009
Externally publishedYes
Event2009 Symposium on VLSI Technology, VLSIT 2009 - Kyoto, Japan
Duration: Jun 16 2009Jun 18 2009

Publication series

NameDigest of Technical Papers - Symposium on VLSI Technology
ISSN (Print)0743-1562

Other

Other2009 Symposium on VLSI Technology, VLSIT 2009
CountryJapan
CityKyoto
Period06/16/0906/18/09

ASJC Scopus subject areas

  • Electrical and Electronic Engineering

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