Gate first band edge hign-k/metal stacks with EOT=0.74nm for 22nm node nFETs

J. Huang*, P. D. Kirsch, Muhammad Mustafa Hussain, D. Heh, P. Sivasubramani, C. Young, D. C. Gilmer, C. S. Park, Y. N. Tan, C. Park, H. R. Harris, P. Majhi, G. Bersuker, B. H. Lee, H. H. Tseng, R. Jammy

*Corresponding author for this work

Research output: Chapter in Book/Report/Conference proceedingConference contributionpeer-review

1 Scopus citations

Abstract

We demonstrate for the first time a gate first high-k/metal gate (MG) nFET with EOT=0.74nm (Tinv=1.15nm), low V, =0.30V, high performance [Ion/Ioff=μA/um) at 100(nA/urn)], low leakage (>200x reduction vs. SiO2/PolySi) and good PBTI. Low-k interface layer scaling and high-k La-doping enable this desirable EOT and Vt. SiON/HfLaSiON can give similar interface quality as SiO2/HfSiON. Device performance was further improved 5% by strain engineering.

Original languageEnglish (US)
Title of host publication2008 International Symposium on VLSI Technology, Systems and Applications, VLSI-TSA
Pages152-153
Number of pages2
DOIs
StatePublished - Aug 14 2008
Event2008 International Symposium on VLSI Technology, Systems and Applications, VLSI-TSA - Hsinchu, Taiwan, Province of China
Duration: Apr 21 2008Apr 23 2008

Publication series

NameInternational Symposium on VLSI Technology, Systems, and Applications, Proceedings

Other

Other2008 International Symposium on VLSI Technology, Systems and Applications, VLSI-TSA
CountryTaiwan, Province of China
CityHsinchu
Period04/21/0804/23/08

ASJC Scopus subject areas

  • Electronic, Optical and Magnetic Materials
  • Condensed Matter Physics
  • Electrical and Electronic Engineering

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