Gate dielectrics for high performance and low power CMOS SoC applications

F. Cubaynes*, C. Dachs, C. Detcheverry, A. Zegers, V. Venezia, J. Schmitz, P. Stolk, M. Jurczak, K. Henson, R. Degraeve, A. Rothschild, T. Conard, J. Petry, M. Da Rold, M. Schaekers, G. Badenes, L. Date, D. Pique, H. Al-Shareef, R. Murto

*Corresponding author for this work

Research output: Chapter in Book/Report/Conference proceedingConference contributionpeer-review

Abstract

This paper investigates the use of plasma nitridation (PN) for fabricating 1.5 and 2 nm gate dielectrics for CMOS system-on-a-chip (SoC) applications. The separate optimisation of PN recipes for high performance (HP, 1.5 nm) and low power (LP, 2 nm) CMOS devices results in good device performance with excellent device lifetime and low 1/f noise. For tripleoxide SoC applications, the use of a common PN step for both HP and LP yields gate dielectrics with excellent breakdown characteristics and devices with the required off-state leakage control.

Original languageEnglish (US)
Title of host publicationEuropean Solid-State Device Research Conference
PublisherIEEE Computer Society
Pages427-430
Number of pages4
ISBN (Electronic)8890084782
DOIs
StatePublished - 2002
Externally publishedYes
Event32nd European Solid-State Device Research Conference, ESSDERC 2002 - Firenze, Italy
Duration: Sep 24 2002Sep 26 2002

Other

Other32nd European Solid-State Device Research Conference, ESSDERC 2002
CountryItaly
CityFirenze
Period09/24/0209/26/02

ASJC Scopus subject areas

  • Electrical and Electronic Engineering
  • Safety, Risk, Reliability and Quality

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