Fabrication of three-dimensional MIS nano-capacitor based on nano-imprinted single crystal silicon nanowire arrays

Yujia Zhai, Marylene Palard, Leo Mathew, Muhammad Mustafa Hussain, Grant Grant Willson, Emanuel Tutuc, Sanjay Kumar Banerjee

    Research output: Contribution to journalArticlepeer-review

    3 Scopus citations

    Abstract

    We report fabrication of single crystalline silicon nanowire based-three-dimensional MIS nano-capacitors for potential analog and mixed signal applications. The array of nanowires is patterned by Step and Flash Imprint Lithography (S-FIL). Deep silicon etching (DSE) is used to form the nanowires with high aspect ratio, increase the electrode area and thus significantly enhance the capacitance. High-! dielectric is deposited by highly conformal atomic layer deposition (ALD) Al2O3 over the Si nanowires, and sputtered metal TaN serves as the electrode. Electrical measurements of fabricated capacitors show the expected increase of capacitance with greater nanowire height and decreasing dielectric thickness, consistent with calculations. Leakage current and time-dependent dielectric breakdown (TDDB) are also measured and compared with planar MIS capacitors. In view of greater interest in 3D transistor architectures, such as FinFETs, 3D high density MIS capacitors offer an attractive device technology for analog and mixed signal applications. - See more at: http://www.eurekaselect.com/105099/article#sthash.EzeJxk6j.dpuf
    Original languageEnglish (US)
    Pages (from-to)333-338
    Number of pages6
    JournalMicro and Nanosystems
    Volume4
    Issue number4
    DOIs
    StatePublished - Nov 26 2012

    ASJC Scopus subject areas

    • Building and Construction

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