Experimental verification of on-chip CMOS fractional-order capacitor emulators

G. Tsirimokou, C. Psychalinos, Khaled N. Salama, A.S. Elwakil

Research output: Contribution to journalArticlepeer-review

52 Scopus citations

Abstract

The experimental results from a fabricated integrated circuit of fractional-order capacitor emulators are reported. The chip contains emulators of capacitors of orders 0.3, 0.4, 0.5, 0.6 and 0.7 with nano-Farad pseudo-capacitances that can be adjusted through a bias current. Two off-chip capacitors are used to set the bandwidth of each emulator independently. The chip was designed in Austria microsystems (AMS) 0.35μ CMOS. © 2016 The Institution of Engineering and Technology.
Original languageEnglish (US)
Pages (from-to)1298-1300
Number of pages3
JournalElectronics Letters
Volume52
Issue number15
DOIs
StatePublished - Jun 13 2016

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