The embedded DSP Blocks in FPGAs have become significantly more capable in recent generations of devices. While vendor synthesis tools can infer the use of these resources, the efficiency of this inference is not guaranteed. Specific language structures are suggested for implementing standard applications but others that do not fit these standard designs can suffer from inefficient synthesis inference. In this paper, we demonstrate this effect by synthesising a number of arithmetic circuits, showing that standard code results in a significant resource and timing overhead compared to considered use of DSP Blocks and their plethora of configuration options through custom instantiation. © 2012 IEEE.
|Original language||English (US)|
|Title of host publication||Proceedings - 22nd International Conference on Field Programmable Logic and Applications, FPL 2012|
|Number of pages||4|
|State||Published - Dec 12 2012|