Enhanced performance and SRAM stability in FinFET with reduced process steps for source/drain doping

J. W. Yang*, H. R. Harris, M. M. Hussain, B. Sassman, H. H. Tseng, R. Jammy

*Corresponding author for this work

Research output: Chapter in Book/Report/Conference proceedingConference contributionpeer-review

10 Scopus citations

Abstract

Improved static noise margin in SRAM of 18% and decreased intrinsic inverter delay of 6% is demonstrated for the first time in double-gate CMOS finFET with gate-source/drain underlap doping. The excellent results are achieved by optimization of the spacer while simplifying the processing of source/drain region by skipping costly implants. Improved circuit and device performance with reduced processing steps malee finFETs a more attractive option for 32nm technology node and beyond.

Original languageEnglish (US)
Title of host publication2008 International Symposium on VLSI Technology, Systems and Applications, VLSI-TSA
Pages20-21
Number of pages2
DOIs
StatePublished - 2008
Externally publishedYes
Event2008 International Symposium on VLSI Technology, Systems and Applications, VLSI-TSA - Hsinchu, Taiwan, Province of China
Duration: Apr 21 2008Apr 23 2008

Other

Other2008 International Symposium on VLSI Technology, Systems and Applications, VLSI-TSA
CountryTaiwan, Province of China
CityHsinchu
Period04/21/0804/23/08

ASJC Scopus subject areas

  • Engineering(all)

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