A CMOS technology-compatible fabrication process for flexible CMOS electronics embedded during additive manufacturing (i.e. 3D printing). A method for such a process may include printing a first portion of a 3D structure; pausing the step of printing the 3D structure to embed the flexible silicon substrate; placing the flexible silicon substrate in a cavity of the first portion of the 3D structure to embed the flexible silicon substrate in the 3D structure; and resuming the step of printing the 3D structure to form the second portion of the 3D structure.
|Original language||English (US)|
|Patent number||WO 2017175159 A1|
|IPC||H01L 33/ 48 A I|
|State||Published - Oct 12 2017|