This paper proposes a structured method for scaling both the supply voltage as well as the body bias voltage for CMOS embedded static memory with the aim of achieving a controllable and dynamic probability of failure with minimum power consumption for each memory block. The target error probability is managed according to the time varying error tolerance attributes of the application using the memory at a certain instant in time. This approach enables system designers to abstract the concepts of power awareness, yield and reliability as design tradeoffs-that incorporate application knowledge-early in the design cycle. The paper develops a formal theoretical and practical foundation based on the underlying device statistics upon which both system and circuit designers can investigate error aware design. © 2010 IEEE.
|Original language||English (US)|
|Journal||IEEE Transactions on Very Large Scale Integration (VLSI) Systems|
|State||Published - Oct 1 2011|