Mapping complex mathematical expressions to DSP blocks through standard inference from pipelined code is inefficient and results in significantly reduced throughput. In this paper, we demonstrate the benefit of considering the structure and pipeline arrangement of DSP blocks during mapping. We have developed a tool that can map mathematical expressions using RTL inference, through high level synthesis with Vivado HLS, and through a custom approach that incorporates DSP block structure. We can show that the proposed method results in circuits that run at around double the frequency of other methods, demonstrating that the structure of the DSP block must be considered when scheduling complex expressions.
|Original language||English (US)|
|Title of host publication||Conference Digest - 24th International Conference on Field Programmable Logic and Applications, FPL 2014|
|Publisher||Institute of Electrical and Electronics Engineers Inc.|
|State||Published - Jan 1 2014|