A performance monitor configured to count memory transactions and to issue an interrupt to the computer system if the monitor detects a specified number of transactions associated with a particular segment of the physical address space of the system. The monitor includes an interface suitable for coupling to an interconnect network of a computer system and configured to extract physical address information from a transaction traversing the interconnect network, a translation module adapted for associating the extracted physical address with one of a plurality of memory blocks and, in response thereto, incrementing a memory block counter corresponding to the memory block, and an interrupt unit configured to assert an interrupt if the block counter exceeds a predetermined value. The interface unit is configurable to selectively monitor either incoming or outgoing transactions and the translation unit preferably includes a plurality of region filters each comprising one or more of the memory blocks. In the preferred embodiment, the plurality of block counters are implemented with a random access memory device. In one embodiment useful for simulating operation of the system and for checking the design of the performance monitor, the monitor further includes a transaction generator coupled to the interconnect network and configured to issue specified remote memory transactions at specified intervals if a monitor enable bit of the performance monitor is disabled. In one embodiment, the transaction generator is configurable to issue either outgoing transactions or incoming transactions.
|Original language||English (US)|
|IPC||G06F 12/ 08 A I|
|State||Published - Dec 24 2002|