Dipole controlled metal gate with hybrid low resistivity cladding for gate-last CMOS with low Vt

Christopher L. Hinkle, Rohit V. Galatage, Richard A. Chapman, Eric M. Vogel, Husam N. Alshareef, Clive M. Freeman, Erich Wimmer, Hiroaki Niimi, Andrei V. Li-Fatou, Judy B. Shaw, James J. Chambers

Research output: Chapter in Book/Report/Conference proceedingConference contribution

13 Scopus citations

Abstract

In this contribution, NMOS and PMOS band edge effective work function (EWF) and correspondingly low Vt are demonstrated using standard fab materials and processes in a gate-last scheme. For NMOS, the use of an Al cladding layer results in Vt = 0.08 V consistent with NMOS EWF = 4.15 eV. Migration of the Al cladding into the TiN and a relatively low oxygen concentration near the TiN/HfO2 interface are responsible for the low EWF. For PMOS, employing a W cladding layer along with a post-TiN anneal in an oxidizing ambient results in elevated oxygen concentration near the TiN/HfO2 interface and Vt = -0.20 V consistent with a PMOS EWF = 5.05 eV. First-principles calculations indicate N atoms displaced from the TiN during the oxidizing anneal form dipoles at the TiN/HfO2 interface that play a critical role in determining the PMOS EWF. © 2010 IEEE.
Original languageEnglish (US)
Title of host publication2010 Symposium on VLSI Technology
PublisherInstitute of Electrical and Electronics Engineers (IEEE)
Pages183-184
Number of pages2
ISBN (Print)9781424476374
DOIs
StatePublished - Jun 2010

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