Design and demonstration of micro-electro-mechanical relay multipliers

Hossein Fariborzi*, Fred Chen, Vladimir Stojanović, Rhesa Nathanael, Jaeseok Jeon, Tsu Jae King Liu

*Corresponding author for this work

Research output: Chapter in Book/Report/Conference proceedingConference contributionpeer-review

24 Scopus citations

Abstract

This paper describes the micro-architecture and circuit techniques for building multipliers with micro-electromechanical (MEM) relays. By optimizing the circuits and micro-architecture to suit relay device characteristics, the performance of the relay based multiplier is improved by a factor of ∼8x over any known static CMOS-style implementation, and ∼4x over CMOS pass-gate equivalent implementations. A 16-bit relay multiplier is shown to offer ∼10x lower energy per operation at sub-10 MOPS throughputs when compared to an optimized CMOS multiplier at an equivalent 90 nm technology node. To demonstrate the viability of this technology, we experimentally demonstrate the operation of the primary multiplier building block: a full (7:3) compressor, built with 98 MEM-relays, which is the largest working MEM-relay circuit reported to date.

Original languageEnglish (US)
Title of host publication2011 Proceedings of Technical Papers
Subtitle of host publicationIEEE Asian Solid-State Circuits Conference 2011, A-SSCC 2011
Pages117-120
Number of pages4
DOIs
StatePublished - Dec 1 2011
Event7th IEEE Asian Solid-State Circuits Conference, A-SSCC 2011 - Jeju, Korea, Republic of
Duration: Nov 14 2011Nov 16 2011

Publication series

Name2011 Proceedings of Technical Papers: IEEE Asian Solid-State Circuits Conference 2011, A-SSCC 2011

Other

Other7th IEEE Asian Solid-State Circuits Conference, A-SSCC 2011
CountryKorea, Republic of
CityJeju
Period11/14/1111/16/11

ASJC Scopus subject areas

  • Hardware and Architecture
  • Electrical and Electronic Engineering

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