Demonstration of integrated micro-electro-mechanical relay circuits for VLSI applications

Matthew Spencer*, Fred Chen, Cheng C. Wang, Rhesa Nathanael, Hossein Fariborzi, Abhinav Gupta, Hei Kam, Vincent Pott, Jaeseok Jeon, Tsu Jae King Liu, Dejan Marković, Elad Alon, Vladimir Stojanović

*Corresponding author for this work

Research output: Contribution to journalArticlepeer-review

141 Scopus citations

Abstract

This work presents measured results from test chips containing circuits implemented with micro-electro-mechanical (MEM) relays. The relay circuits designed on these test chips illustrate a range of important functions necessary for the implementation of integrated VLSI systems and lend insight into circuit design techniques optimized for the physical properties of these devices. To explore these techniques a hybrid electro-mechanical model of the relays' electrical and mechanical characteristics has been developed, correlated to measurements, and then also applied to predict MEM relay performance if the technology were scaled to a 90 nm technology node. A theoretical, scaled, 32-bit MEM relay-based adder, with a single-bit functionality demonstrated by the measured circuits, is found to offer a factor of ten energy efficiency gain over an optimized CMOS adder for sub-20 MOPS throughputs at a moderate increase in area.

Original languageEnglish (US)
Article number5617293
Pages (from-to)308-320
Number of pages13
JournalIEEE Journal of Solid-State Circuits
Volume46
Issue number1
DOIs
StatePublished - Jan 1 2011

Keywords

  • Adders
  • MEM relays
  • digital circuits
  • microelectromechanical devices
  • minimum energy point
  • very-large-scale integration

ASJC Scopus subject areas

  • Electrical and Electronic Engineering

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