Demonstration of high performance transistors with PVD metal gate

H. R. Harris*, H. C. Wen, K. Choi, Husam Niman Alshareef, H. Luan, Y. Senzaki, C. D. Young, S. C. Song, Z. Zhang, G. Bersuker, P. Majhi, B. H. Lee

*Corresponding author for this work

Research output: Chapter in Book/Report/Conference proceedingConference contributionpeer-review

Abstract

Transistors devices have been fabricated in the traditional gate-first approach with HfO2 and PVD TaN as the gate electrode. The stability of the PVD metal with the high dielectric constant material is studied in terms of the gate leakage, capacitance, transistor properties and reliability. Comparison of the PVD devices with the same devices using ALD TaN is performed to understand the influence of the PVD process on device properties. It is concluded that PVD deposition of metal gates with 1000oC poly activation anneal can be performed with no measurable damage to the dielectric and full thermal stability. Furthermore, one can realize high performance transistors with proper engineering of the PVD process

Original languageEnglish (US)
Title of host publicationProceedings of ESSDERC 2005
Subtitle of host publication35th European Solid-State Device Research Conference
Pages431-434
Number of pages4
DOIs
StatePublished - Dec 1 2005
EventESSDERC 2005: 35th European Solid-State Device Research Conference - Grenoble, France
Duration: Sep 12 2005Sep 16 2005

Publication series

NameProceedings of ESSDERC 2005: 35th European Solid-State Device Research Conference
Volume2005

Other

OtherESSDERC 2005: 35th European Solid-State Device Research Conference
CountryFrance
CityGrenoble
Period09/12/0509/16/05

ASJC Scopus subject areas

  • Engineering(all)

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