This paper shows that by co-designing circuits and systems, considerable power savings are possible if the inherent data redundancy of candidate systems such as wireless is used to compensate for hardware failures. A comprehensive study of 6T SRAM failure modes is presented. The generated statistics are used to quantify a power savings of up to 17.5% for a case study of a 32 nm CMOS 3GPP WCDMA modem. © 2007 IEEE.
|Original language||English (US)|
|Title of host publication||Proceedings - Eighth International Symposium on Quality Electronic Design, ISQED 2007|
|State||Published - Aug 28 2007|